CPUs with addressable cache? I was wondering if is there…
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CPUs with addressable cache?
I was wondering if is there any CPUs/OSes where at least some part of the L1/L2 cache is addressable like normal memory, something like:
- Caches would be accessible with pointers like normal memory
- Load/Store operations could target either main memory, registers or a cache level (e.g.: load from RAM to L1, store from registers to L2)
- The OS would manage allocations like with memory
- The OS would manage coherency (immutable/mutable borrows, collisions, writebacks, synchronization, ...)
- Pages would be replaced by cache lines/blocks
I tried to search google but probably I'm using the wrong keywords so unrelated results show up.
#technology
I was wondering if is there any CPUs/OSes where at least some part of the L1/L2 cache is addressable like normal memory, something like:
- Caches would be accessible with pointers like normal memory
- Load/Store operations could target either main memory, registers or a cache level (e.g.: load from RAM to L1, store from registers to L2)
- The OS would manage allocations like with memory
- The OS would manage coherency (immutable/mutable borrows, collisions, writebacks, synchronization, ...)
- Pages would be replaced by cache lines/blocks
I tried to search google but probably I'm using the wrong keywords so unrelated results show up.
#technology
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